The present invention relates generally to inverter power conversion systems such as those used to supply variable frequency alternating current power to an electric motor and more particularly to such systems having improved control means.
It has been known for many years to provide variable power and frequency alternating current (a.c.) to a load through the use of a bridge arrangement of controlled rectifiers. Originally, the rectifiers employed in such bridges were usually gas tube devices such as thyratrons but it is now much more common to use semiconductor devices of the gate control type which are generically known as thyristors, the most common form of which is the silicon controlled rectifier. For convenience and purposes of this description, the term thyristor will be used as a generic term.
In one of the more common three phase versions of the inverter bridge, variable direct current (d.c.) power is applied to a six thyristor bridge having a pair of series thyristors associated with each leg of the three phase output. An inverter control supplies gate pulses to gate the thyristors on at the desired frequency for the inverter output. One very common form of control which is known in the art includes an oscillator which outputs pulses at a frequency six times that desired for the output of the inverter (one pulse per thyristor per cycle). The actual gating pulses used to render the thyristors conductive are derived from a recirculating shift register having six bit positions. The contents of the register are shifted one bit position with each application of a timing pulse and in a direction determined by a direction signal signifying whether the inverter is to run in the forward or reverse mode.
In allowed United States Patent Application Ser. No. 895,136, filed Aug. 10, 1978, "Reversible Variable Frequency Oscillator For Smooth Reversing of AC Motor Drives" by P. M. Espelage et al, which application is assigned to the assignee of the present invention and which application is specifically incorporated hereinto by reference, there is described a control for a controlled current inverter drive which is designed to operate on a command signal having a relatively small d.c. component representing the desired frequency and a relatively large ripple component. The system described in that application employs an integrator for receiving an input command signal as described above and which further has a polarity designating the desired mode of operation. The output of the integrator is essentially a ramp function which is applied to two comparator circuits which sense, respectively, positive and negative going ramp signals. When the ramp signal reaches a predetermined magnitude as determined by the comparator circuit, there is provided as an output signal a timing pulse which first serves to reset the integrator and which also serves, depending upon whether the timing pulse is from the positive or negative side of the system, to set a direction flip-flop the output of which provides the direction signal to a recirculating shift register. After a short delay to allow the direction flip-flop to set and apply direction signal to the recirculating shift register, the timing pulse is applied to the shift register to cause the contents thereof to shift. The extant content of the shift register is used to initiate the gating signals for the thyristors.
While the above described system works very well with components which are built to very close tolerances and for low frequency operations, there are several factors which make the system less than totally satisfactory for high frequency commercial applications. These factors consist, essentially, of the use of the directional flip-flop in conjunction with the delay network used to delay the application of the timing signals to the shift register so as to allow sufficient time for the direction signal to be applied. This delay, particularly at high frequencies, has a tendency to appear as a change of frequency which results in linearity errors which are not always acceptable. In addition, because the allowable times were short, the high frequency flip-flops required are basically noise sensitive by nature. Hence, to reduce noise sensitivity, it is necessary to include a considerable amount of filtering which, in turn, reduces the operational speed of the flip-flop and hence increases the non-linearity errors.